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16 - bit , isolated sigma - delta modulator data sheet ad7403 features 5 mhz to 20 mhz external clock input rate 16 bits, no missing codes signal - to - noise ratio (snr): 88 db typical effective number of bits (enob): 14.2 bits typical offset drift vs. temperature ad7403 : 1.6 v/c typical ad7403 - 8 : 2 v/c typical on - board digital isolator on - board reference full - sca le analog input range: 320 mv operating range ad7403 : ?40c to + 125c ad7403 - 8 : ?40c to + 105c high common - mode transient immunity: >25 kv/s wide - body soic with increased creepage package slew rate limited output for low emi safety and regulatory approvals ul recognition 5000 v rms for 1 minute per ul 1577 csa component accepta nce notice 5a vde certificate of conformity din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 v iorm = 1250 v peak applications shunt current monitoring ac motor controls power and solar inverters wind turbine inverters data acquisition systems analog - to - digital and opto isolator replacements functional block dia gram v dd1 v dd2 ad7403 buf ref clk decoder gnd 1 gnd 2 md a t mclkin (5mhz t o 20mhz) 12196-001 v in+ v in? clk encoder d at a encoder d at a decoder - adc figure 1. general description the ad7403 1 is a high performance, second - order, - modulator that convert s an analog input signal into a high speed, single - bit data stream, with on - chip digital isolation based on analog devices, inc., i coupler? technology. the device operate s from a 5 v (v dd1 ) power supply and accept s a differential input signal of 250 mv (3 20 mv full - scale). the diffe rential input is ideally suited to shunt voltage monitori ng in high voltage applications where galvanic isolation is required. the analog input is continuously sampled by a high performance analog modulator, and converted to a ones density digital output stream with a data rate of up to 20 mhz. the original information can be reconstructed with an appropriate digital filter to achieve 88 db signal to noise ratio (snr) at 78.1 ksps. the serial input/output can use a 5 v or a 3 v supply (v dd2 ). the serial interface is digitally isolated. high speed complementary metal oxide semiconductor (cmos) technology , combined with monolithic transformer technology, means the on - chip isolation provides outstanding performance characteristics, superior to alternatives such as optocoupler devices. the ad7403 device is offered in a 16 - lead, wide - body soic package and has an oper - ating temperature range of ?40c to +125 c. the ad7403 - 8 device is offered in an 8 - lead, wide - body soic package and has an operating temperature range of ?40c to +105c. 1 protected by u.s. patents 5,952,849; 6,873,065; and 7,075,329. rev. b document feedback information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications sub ject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 ? 2014 C 2015 analog devices, inc. all rights reserved. technical support www.analog.com
ad7403* product page quick links last content update: 11/01/2016 comparable parts view a parametric search of comparable parts evaluation kits ? ad-fmcmotcon2-ebz evaluation board ? ad7403 evaluation board ? evaluation board for evaluating flexmc motor control low voltage kit ? evaluation board for evaluating flexmc motor control universal ac kit ? isolated inverter platform evaluation board documentation application notes ? an-1316: generating multiple isolated bias rails for igbt motor drives with flyback, sepic, and ?uk combination ? an-1377: gain and offset temperature drift compensation for the ad7403/ad7405 data sheet ? ad7403-ep: enhanced product data sheet ? ad7403: 16-bit, isolated sigma-delt modulator data sheet user guides ? ug-683: evaluating the ad7403 16-bit, isolated sigma- delta adc software and systems requirements ? eval-fmcmotcon2 evaluation software tools and simulations ? ad7403 matlab model ? ad7403 ibis model ? ad7403-8 ibis model reference materials informational ? adsp-cm40x in solar pv inverters press ? highest accuracy isolated sigma-delta modulator increases efficiency of motor drives and power inverters technical articles ? a networked approach to improving energy efficiency in manufacturing automation systems ? a system approach to understanding the impact of nonideal effects in a motor drive current loop ? functional safety for integrated circuits used in variable speed drives ? ms-2652: measurement techniques for industrial motion control ? ms-2758: enhancing industrial motor control performance utilizing digital isolator technology ? sigma-delta conversion used for motor control design resources ? ad7403 material declaration ? pcn-pdn information ? quality and reliability ? symbols and footprints discussions view all ad7403 engineerzone discussions sample and buy visit the product page to see pricing options technical support submit a technical question or find your regional support number * this page was dynamically generated by analog devices, inc. and inserted into this data sheet. note: dynamic changes to the content on this page does not constitute a change to the revision number of the product data sheet. this content may be frequently modified.
ad7403 data sheet rev. b | page 2 of 24 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 functional block diagram .............................................................. 1 general description ......................................................................... 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 ad7403 .......................................................................................... 3 ad7403-8 ...................................................................................... 4 timing specifications .................................................................. 5 package characteristics ............................................................... 6 insulation and safety related specifications ............................ 6 regulatory information ............................................................... 6 din v vde v 0884-10 (vde v 0884-10):2006-12 insulation characteristics .............................................................................. 7 absolute maximum ratings ............................................................ 8 esd caution .................................................................................. 8 pin configurations and function descriptions ........................... 9 typical performance characteristics ........................................... 10 terminology .................................................................................... 14 theory of operation ...................................................................... 15 circuit information .................................................................... 15 analog input ............................................................................... 15 differential inputs ...................................................................... 16 digital output ............................................................................. 16 applications information .............................................................. 17 current sensing applications ................................................... 17 voltage sensing applications .................................................... 17 input filter ................................................................................... 18 digital filter ................................................................................ 18 interfacing to adsp-cm4xx .................................................... 21 power supply considerations ................................................... 21 grounding and layout .............................................................. 21 insulation lifetime ..................................................................... 21 outline dimensions ....................................................................... 23 ordering guide .......................................................................... 24 revision history 5/15rev. a to rev. b added ad7403-8 ................................................................ universal added endnote 3, table 1 ............................................................... 4 added table 2; renumbered sequentially .................................... 4 added figure 4 .................................................................................. 7 added figure 6 and table 11........................................................... 9 added figure 8 ................................................................................ 10 added figure 14 and figure 18..................................................... 11 added figure 20 .............................................................................. 12 added power supply considerations section, figure 41, and figure 42 .......................................................................................... 21 added figure 47, outline dimensions ........................................ 23 changes to ordering guide .......................................................... 24 11/14rev. 0 to rev. a change to figure 1 ............................................................................ 1 changes to regulatory information section and table 5 ............ 5 changes to table 7 ............................................................................. 7 changes to ordering guide .......................................................... 20 4/14revision 0: initial version
data sheet ad7403 specifications ad7403 v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in+ = ?250 mv to +250 mv, v in? = 0 v, t a = ?40c to +125c, f mclkin 1 = 5 mhz to 20 mhz, tested with sinc3 filter, 256 decimation rate, as defined by verilog code, unless otherwise noted. all voltages are relative to their respective ground. table 1 . parameter min typ max unit test conditions/comments static performance resolution 16 bits filter output truncated to 16 bits integral nonlinearity (inl) 2 2 12 lsb differential nonlinearity (dnl) 2 0.99 lsb guaranteed no missed codes to 16 bits offset error 2 0.2 0.75 mv offset drift vs. temperature 3 1.6 3.8 v/c 1.3 3.1 v/c 0c to 85c offset drift vs. v dd1 3 50 v/v gain error 2 0.2 0.8 % fsr f mclkin = 16 mhz 0.2 0.8 % fsr f mclkin = 20 mhz, t a = ?40c to +85c 0.2 1.2 % fsr f mclkin = 20 mhz gain error drift vs. temperature 3 65 95 ppm/c 40 60 v/c gain error drift vs. v dd1 3 0.6 mv/v analog input input voltage range ?320 +320 mv full - scale range ?250 +250 mv for specified performance input common - mode voltage range ?200 to +300 mv dynamic input current 45 50 a v in + = 250 mv, v in ? = 0 v 0.05 a v in + = 0 v, v in ? = 0 v dc leakage current 0.01 0.6 a input capacitance 14 pf dynamic specifications v in + = 1 khz signal - to - noise - and - distortion ratio (sinad) 2 81 87 db 83 87 db ?40c to +85c signal -to - noise ratio (snr) 2 86 88 db total harmonic distortion (thd) 2 ?96 db peak harmonic or spurious noise (sfdr) 2 ?97 db effective number of bits (enob) 2 13.1 14.2 bits 13.4 14.2 bits ?40c to +85c noise free code resolution 2 14 bits isolation transient immunity 2 25 30 kv/s logic inputs cmos with schmitt trigger input high voltage (v ih ) 0.8 v dd2 v input low voltage (v il ) 0.2 v dd2 v input current (i in ) 0.6 a input capacitance (c in ) 10 pf logic outputs output high voltage (v oh ) v dd2 ? 0.1 v i o = ?200 a output low voltage (v ol ) 0.4 v i o = +200 a rev. b | page 3 of 24
ad7403 data sheet parameter min typ max unit test conditions/comments power requirements v dd1 4.5 5.5 v v dd2 3 5.5 v i dd1 30 36 ma v dd1 = 5.5 v i dd2 12 18 ma v dd2 = 5.5 v 6 10 ma v dd2 = 3.3 v power dissipation 231 297 mw v dd1 = v dd2 = 5.5 v 185 231 mw v dd1 = 5.5 v, v dd2 = 3.3 v 1 for f mcl kin > 16 mhz , mark space ratio is 48/52 to 52/48, v dd1 = 5 v 5%. 2 see the terminology section . 3 not production tested. sample tested during initial release to e nsure compliance. ad7403 - 8 v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, v in+ = ?250 mv to +250 mv, v in? = 0 v, t a = ?40c to +105c, f mclkin 1 = 5 mhz to 20 mhz, tested with sinc3 filter, 256 decimation rate, as defined by verilog code, unless otherwise noted. all voltages are relative to their respective groun d. table 2 . parameter min typ max unit test conditions/comments static performance resolution 16 bits filter output truncated to 16 bits integral nonlinearity (inl) 2 2 6.5 lsb differential nonlinearity (dnl) 2 0.99 lsb guaranteed no missed codes to 16 bits offset error 2 1 1.7 mv offset drift vs. temperature 3 2 6.8 v/c offset drift vs. v dd1 3 425 v/v gain error 2 0.2 0.8 % fsr f mclkin = 16 mhz 0.2 1.4 % fsr f mclkin = 20 mhz gain error drift vs. temperature 3 32 80 ppm/c 20 51 v/c gain error drift vs. v dd1 3 0.2 mv/v analog input input voltage range ?320 +320 mv full - scale range ?250 +250 mv for specified performance input common - mode voltage range ?200 to +300 mv dynamic input current 45 50 a v in+ = 250 mv, v in? = 0 v 0.05 a v in+ = 0 v, v in? = 0 v dc leakage current 0.01 0.6 a input capacitance 14 pf dynamic specifications v in+ = 1 khz signal - to - noise - and - distortion ratio (sinad) 2 82 87 db signal -to - noise ratio (snr) 2 86 88 db total harmonic distortion (thd) 2 ?94 db peak harmonic or spurious noise (sfdr) 2 ?94 db effective number of bits (enob) 2 13.3 14.2 bits isolation transient immunity 2 25 30 kv/s logic inputs cmos with schmitt trigger input high voltage (v ih ) 0.8 v dd2 v input low voltage (v il ) 0.2 v dd2 v input current (i in ) 0.6 a input capacitance (c in ) 10 pf logic outputs output high voltage (v oh ) v dd2 ? 0.1 v i o = ?200 a output low voltage (v ol ) 0.4 v i o = +200 a rev. b | page 4 of 24
data sheet ad7403 rev. b | page 5 of 24 parameter min typ max unit test conditions/comments power requirements v dd1 4.5 5.5 v v dd2 3 5.5 v i dd1 30 33.5 ma v dd1 = 5.5 v i dd2 13 16 ma v dd2 = 5.5 v 6.5 8 ma v dd2 = 3.3 v power dissipation 237 272 mw v dd1 = v dd2 = 5.5 v 187 211 mw v dd1 = 5.5 v, v dd2 = 3.3 v 1 for f mclkin > 16 mhz, mark space ratio is 48/52 to 52/48, v dd1 = 5 v 5%. 2 see the terminology section. 3 not production tested. sample tested duri ng initial release to ensure compliance. timing specifications v dd1 = 4.5 v to 5.5 v, v dd2 = 3 v to 5.5 v, t a = ?40c to +105c ( ad7403-8 ) or ?40c to +125c ( ad7403 ), unless otherwise noted. sample tested during initial release to ensure compliance. it is recommended to read mdat on the mclkin rising edge. table 3. parameter limit at t min , t max unit description min typ max f mclkin 5 mhz master clock input frequency 20 mhz t 1 1 data access time after mclkin rising edge 40 ns v dd2 = 4.5 v to 5.5 v 45 ns v dd2 = 3 v to 3.6 v, ad7403 42 ns v dd2 = 3 v to 3.6 v, ad7403-8 t 2 1 data hold time after mclkin rising edge 12 ns v dd2 = 4.5 v to 5.5 v 17 ns v dd2 = 3 v to 3.6 v t 3 master clock low time 0.45 t mclkin ns f mclkin 16 mhz 0.48 t mclkin ns 16 mhz < f mclkin 20 mhz t 4 master clock high time 0.45 t mclkin ns f mclkin 16 mhz 0.48 t mclkin ns 16 mhz < f mclkin 20 mhz 1 defined as the time required from an 80% mclkin input level to when the output crosses 0.8 v or 2.0 v for v dd2 = 3 v to 3.6 v or when the output crosses 0.8 v or 0.7 v dd2 for v dd2 = 4.5 v to 5.5 v as outlined in figure 2. measured with a 200 a load and a 25 pf load capacitance. mclkin mdat 1 see note 1 of table 3 for further details. t 4 t 1 t 2 t 3 80% 2.0v or 0.7 v dd2 1 0.8v 12196-002 figure 2. data timing
ad7403 data sheet package characteristics table 4 . parameter symbol min typ max unit test conditions/comments resistance (input to output) 1 r i- o 10 12 ? capacitance (input to output) 1 c i- o 2.2 pf f = 1 mhz ic junction to ambient thermal resistance ja 45 c/w thermocouple located at center of package underside, test conducted on 4 - layer board with thin traces 1 the device is considered a 2 - terminal device. for ad7403 , pin 1 to p in 8 are shorted together and pin 9 to pin 16 are shorted together. for ad7403 - 8 , pin 1 to pin 4 are shorted together, pin 5 to pin 8 are shorted together. insulation and safet y related specificat ions table 5 . parameter symbol value unit test conditions/comments input to output momentary withstand voltage v iso 5000 min v 1 minute duration minimum external air gap (clearance) ad7403 l(i01) 8.3 min 1 , 2 mm measured from input terminals to output terminals, shortest distance through air ad7403 -8 l(i01) 8.1 min 1 , 2 mm measured from input terminals to output terminals, shortest distance through air minimum external tracking (creepage) ad7403 l(i02) 8.3 min 1 mm measured from input terminals to output terminals, shortest distance path along body ad7403 -8 l(i02) 8.1 min 1 mm measured from input terminals to output terminals, shortest distance path along body minimum internal gap (internal clearance) 0.034 min mm distance through insulation tracking resistance (comparative tracking index) cti >400 v din iec 112/vde 0303 part 1 3 isolation group ii material group (din vde 0110, 1/89, table i) 3 1 in accordance with iec 60950 - 1 guidel ines for the measurement of creepage and clearance distances for a pollution degree of 2 and altitudes 2000 m . 2 consideration must be given to pad layout to ensure the minimum required distance for clearance is maintained. 3 csa cti rating for the ad7403 is >600 v and a material group i isolation group. ad7403 - 8 is >400 and a material group ii isolation group. regulatory informati on table 6 . ul 1 csa vde 2 recognized under 1577 component recognition program 1 approved under csa component acceptance notice 5a certified according to din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 2 5000 v rms isolation voltage single protection basic insulation per csa 60950 -1 - 07 and iec 60950 -1, ad7403 : 830 v rms (1173 v peak ), ad7403 -8 : 810 vrms (1145 v peak ) maximum working voltage 3 reinforced insulation per din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12, 1250 v peak reinforced insulation per csa 60950- 1 - 07 and iec 60950 -1. ad7403 : 415 v rms (586 v peak ), ad7403 -8 : 405 v rms (583 v peak ) maximum working voltage 3 reinforced insulation per iec 60601 - 1, 250 v rms (353 v peak ) maximum working voltage file e214100 file 205078 file 2471900 - 4880 - 0001 1 in accordance with ul 1577, each ad7403 is proof tested by applying an insulation test voltage 6000 v rms for 1 second (current leakage detection limit = 15 a). 2 in accordance with din v vde v 0884 - 10, each ad74 03 is proof tested by applyi ng an insulation test voltage 2344 v peak for 1 sec ond (partial d ischarge detection limit = 5 pc). 3 rating is calculated for a pollution degree of 2 and a material group iii. the ad7403 ri - 16- 2 package material is rated by csa to a cti of >600 v and therefore material group i. the ad7403 - 8 ri - 8 - 1 package material is rated by csa to a cti of >400 v and therefore material group ii. rev. b | page 6 of 24
data sheet ad7403 din v vde v 0884 - 10 (vde v 0884 - 10):2006 - 12 insulation charac teristics this isolator is suitable for reinforced electrical isolation only within the safety limit data. maintenance of the safety da ta is ensured by means of protective circuits. table 7 . description symbol characteristic unit installation classification per din vde 0110 for rated mains voltage 300 v rms i to iv for rated mains voltage 450 v rms i to iv for rated mains voltage 600 v rms i to iv for rated mains voltage 1000 v rms i to iv climatic classification 40/105/21 pollution degree (din vde 0110, table 1) 2 maximum working insulation voltage v iorm 1250 v peak input to output test voltage, method b1 v iorm 1.875 = v pr , 100% production test, t m = 1 second, partial discharge < 5 pc v pd(m) 2344 v peak input to output test voltage, method a v pr(m) after environmental test subgroup 1 v iorm 1.6 = v pr , t m = 60 seconds, partial discharge < 5 pc 2000 v peak after input and/or safety test subgroup 2/ safety test subgroup 3 v iorm 1.2 = v pr , t m = 60 seconds, partial discharge < 5 pc 1500 v peak highest allowable overvoltage (transient overvoltage, t tr = 10 seconds) v iotm 8000 v peak surge isolation voltage v iosm v peak 1.2 s rise time, 50 s, 50% fall time 12000 v peak safety limiting values (maximum value allowed in the event of a failure, see figure 3 and figure 4 ) case temperature t s 150 c side 1 (p vdd1 ) and side 2 (p vdd2 ) power dissipation p so ad7403 2.78 w ad7403 -8 1.19 w insulation resistance at t s , v io = 500 v r io >10 9 ? 0 1 2 3 4 0 50 100 150 200 safe oper a ting power (w) ambient temper a ture (c) 12196-003 figure 3. ad7403 thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 12196-041 safe operating power (w) ambient temperature (c) 0 0 1 2 50 100 150 200 figure 4. ad7403 - 8 thermal derating curve, dependence of safety limiting values with case temperature per din v vde v 0884 - 10 rev. b | page 7 of 24
ad7403 data sheet absolute maximum rat ings t a = 25c, unless otherwise noted. all voltages are relative to their respective ground. table 8 . parameter rating v dd1 to gnd 1 ?0.3 v to +6.5 v v dd2 to gnd 2 ?0.3 v to +6.5 v analog input voltage to gnd 1 ?1 v to v dd1 + 0.3 v digital input voltage to gnd 2 ?0.3 v to v dd2 + 0.5 v output voltage to gnd 2 ?0.3 v to v dd2 + 0.3 v input current to any pin except supplies 1 10 ma operating temperature range ad7403 ?40c to +125c ad7403 -8 ?40c to +105c storage temperature range ?65c to +150c junction temperature 150c pb - free temperature, soldering reflow 260c esd 2 kv ficdm 2 1250 v hbm 3 4000 v 1 transient currents of up to 100 ma do not cause scr to latch up. 2 jesd22 - c101; rc network: 1 ? , cpkg; class: iv . 3 esda/jedec js - 001- 2011; rc network: 1.5 k ? , 100 pf; class: 3a . stresses at or above those listed under absolute maximum ratings may cause permanent damage to the product. this is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. operation beyond the maximum operatin g conditions for extended periods may affect product reliability. table 9 . maximum continuous working voltage 1 parameter max unit constraint ac voltage bipolar waveform 1250 v peak 20 - year minimum lifetime (vde approved working voltage) unipolar waveform 1250 v peak 20- year minimum lifetime dc voltage 1250 v peak 20- year minimum lifetime 1 refers to continuous voltage magnitude imposed across the isolation barrier. esd caution rev. b | page 8 of 24
data sheet ad7403 pin configuration s and function descrip tions v dd1 1 v in+ 2 v in? 3 gnd 1 4 gnd 2 16 nic 2 15 v dd2 14 mclkin 13 nic 1 5 nic 2 12 nic 1 6 mda t 1 1 v dd1 7 nic 2 10 gnd 1 8 gnd 2 9 1 nic = not internal l y connected. connect t o v dd1 , gnd 1 , or le a ve flo a ting. 2 nic = not internal l y connected. connect t o v dd2 , gnd 2 , or le a ve flo a ting. ad7403 t op view (not to scale) 12196-004 figure 5. ad7403 pin configuration table 10. ad7403 pin function descriptions pin no. mnemonic description 1, 7 v dd1 supply voltage, 4.5 v to 5.5 v. this is the supply voltage for the isolated side of the ad7403 and is relative to gnd 1 . for device operation, connect the supply voltage to both pin 1 and pin 7. decouple each supply pin to gnd 1 with a 10 f capacitor in parallel with a 1 nf capacitor. 2 v in+ positive analog input. 3 v in? negative analog input. normally connected to gnd 1 . 4, 8 gnd 1 ground 1. this pin is the ground reference point for all circuitry on the isolated side. 5, 6 nic not internally connected. these pins are not internally connected. connect to v dd1 , gnd 1 , or leave floating. 9, 16 gnd 2 ground 2. this pin is the ground reference point for all circuitry on the nonisolated side. 10, 12, 15 nic not internally connected. these pins are not internally connected. connect to v dd2 , gnd 2 , or leave floating. 11 m dat serial data output. the single bit modulator output is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the mclkin input and are valid on the following mclkin rising edge. 13 mclkin master clock logic input. 5 mhz to 20 mhz frequency range. the bit stream from the modulator is propagated on the rising edge of the mclkin. 14 v dd2 supply voltage, 3 v to 5.5 v. this is the supply voltage for the nonisolated side and is relative to gnd 2 . decouple this supply to gnd 2 with a 100 nf capacitor. v dd1 1 v dd2 v in+ 2 v in? 3 gnd 1 4 8 7 6 mclkin mda t gnd 2 5 ad7403-8 t op view (not to scale) 12196-038 figure 6. ad7403 - 8 pin configuration table 11. ad7403 -8 pin function descriptions pin no. mnemonic description 1 v dd1 supply voltage, 4.5 v to 5.5 v. this is the supply voltage for the isolated side of the ad7403 - 8 and is relative to gnd 1 . for device operation, connect the supply voltage to both pin 1 and pin 7. decouple each supply pin to gnd 1 with a 10 f capacitor in parallel with a 1 nf capacitor. 2 v in+ positive analog input. 3 v in? negative analog input. normally connected to gnd 1 . 4 gnd 1 ground 1. this pin is the ground reference point for all circuitry on the isolated side. 5 gnd 2 ground 2. this pin is the ground reference point for all circuitry on the nonisolated side. 6 mdat serial data output. the single bit modulator outp ut is supplied to this pin as a serial data stream. the bits are clocked out on the rising edge of the mclkin input and are valid on the following mclkin rising edge. 7 mclkin master clock logic input. 5 mhz to 20 mhz frequency range. the bit stream from the modulator is propagated on the rising edge of the mclkin. 8 v dd2 supply voltage, 3 v to 5.5 v. this is the supply voltage for the nonisolated side and is relative to gnd 2 . decouple this supply to gnd 2 with a 100 nf capacitor. rev. b | page 9 of 24
ad7403 data sheet typical performance char acteristics t a = 25c , v dd1 = 5 v, v dd2 = 5 v, v in + = ?250 mv to +250 mv, v in? = 0 v, f mclkin = 20 mhz, using a sinc3 filter with a 256 oversampling ratio (osr), unless otherwise noted. ?120 ?100 ?80 ?60 ?40 ?20 0 psrr (db) 200 m v p-p s i n e w av e on v dd 1 1n f d e c o u p l i n g 12196-005 m c l k i n = 20 m h z m c l k i n = 10 m h z supply ripple frequency (hz) 0 200k 400k 600k 800k 1m figure 7. ad7403 psrr vs. supply ripple frequency 12196-042 psrr (db) supply ripple frequency (hz) ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 200k 400k 600k 800k 1m 200mv p-p sine wave on v dd1 1nf decoupling mclkin = 20mhz mclkin = 10mhz figure 8. ad7403 - 8 psrr vs. supply ripple frequency ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 100 1k 10k 100k 1m cmrr (db) ripple frequenc y (hz) s ho r t e d i n p u t s 200 m v p-p s i n e w av e on i n p u t s mclkin = 2 0 m h z , s i n c 3 decim a tion r a te = 2 5 6 mclkin = 1 0 m h z , s i n c 3 decim a tion r a te = 2 5 6 mclkin = 2 0 m h z , u n f il t e r e d 12196-006 mclkin = 1 0 m h z , u n f il t e r e d figure 9 . cmrr vs. common - mode ripple frequency 70 72 74 76 78 80 82 84 86 88 90 100 1k 10k sinad (db) analog input frequency (hz) 16mhz mclkin, v dd1 = 4.5v 16mhz mclkin, v dd1 = 5.0v 16mhz mclkin, v dd1 = 5.5v 20mhz mclkin, v dd1 = 4.5v 20mhz mclkin, v dd1 = 5.0v 20mhz mclkin, v dd1 = 5.5v 12196-007 figure 10 . sinad vs. analog input frequency ?160 ?140 ?120 ?100 ?80 ?60 ?40 ?20 0 0 5 10 15 20 25 30 magnitude (db) frequenc y (khz) s n r = 88 . 6db f in = 1khz s i n a d = 88 . 3db t hd = ?100 . 5db 12196-008 figure 11 . typical fast fourier transform (fft) 0 10 20 30 40 50 60 dn l error (lsb) code (k) 12196-009 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 figure 12 . typical dnl error rev. b | page 10 of 24
data sheet ad7403 0 10 20 30 40 50 60 in l error (lsb) code (k) 12196-010 ?1.0 ?0.8 ?0.6 ?0.4 ?0.2 0 0.2 0.4 0.6 0.8 1.0 figure 13 . ad7403 typical inl error 12196-043 inl error (lsb) code (k) ?1.5 ?1.0 ?0.5 0 0.5 1.0 0 10 20 30 40 50 60 figure 14 . ad7403 - 8 typical inl error 0 1147 144470 692381 160941 1061 0 0 100 200 300 400 500 600 700 800 32764 32765 32766 32767 32768 32769 32770 hits per code (k) code mclkin = 10mhz v in+ = v in? = 0v 1m samples 12196-011 figure 15 . histogram of codes at code center 60 70 80 100 90 ?50 ?25 0 25 50 75 100 125 150 snr and sinad (db) temper a ture (c) s n r s i n ad 12196-012 f in = 1khz figure 16 . snr and sinad vs. temperature ?120 ? 1 10 ?100 ?90 ?80 ?70 ?60 ?50 ?25 0 25 50 75 100 125 150 thd and sfdr (db) temper a ture (c) t h d s f dr 12196-013 f in = 1khz figure 17 . ad7403 thd and sfdr vs. temperature 12196-044 thd and sfdr (db) temperature (c) ?120 ?110 ?100 ?90 ?80 ?70 ?60 ?50 ?25 0 25 50 75 100 125 thd sfdr f in = 1khz figure 18 . ad7403 - 8 thd and sfdr vs. temperature rev. b | page 11 of 24
ad7403 data sheet ?200 ?150 ?100 ?50 0 50 100 150 200 ?50 ?25 0 25 50 75 100 125 150 offset (v) temper a ture (c) m c l k i n = 20 m h z 12196-014 figure 19 . ad7403 offset vs. temperature 12196-045 offset (v) temperature (c) ?400 ?200 0 200 400 600 800 ?50 ?25 0 25 50 75 100 125 mclkin = 10mhz mclkin = 16mhz mclkin = 20mhz figure 20 . ad7403 - 8 offset vs. temperature ?10 ?8 ?6 ?4 ?2 0 2 4 6 8 10 ?50 ?25 0 25 50 75 100 125 150 gain error (mv) temper a ture (c) mc l k i n = 10 m h z mc l k i n = 20 m h z 12196-015 figure 21 . gain error vs. temperature 0 5 10 15 20 25 30 35 4.50 4.75 5.00 5.25 5.50 i dd1 (ma) v dd1 (v) mc l k i n = 20 m h z , ?40 c mc l k i n = 20 m h z , +2 5 c mc l k i n = 20 m h z , +8 5 c mc l k i n = 20 m h z , +1 2 5 c mc l k i n = 10 m h z , ?40 c mc l k i n = 10 m h z , +2 5 c mc l k i n = 10 m h z , +8 5 c mc l k i n = 10 m h z , +1 2 5 c 12196-016 figure 22 . i dd1 vs. v dd1 at various temperatures and clock rates 25 26 27 28 29 30 31 32 ?250 ?125 0 125 250 i dd1 (ma) v in+ dc input (mv) d c i n p u t t a = ?40 c t a = 0 c t a = +2 5 c t a = +8 5 c t a = +1 2 5 c 12196-017 figure 23 . i dd1 vs. v in+ dc input at various temperatures 0 2 4 6 8 10 12 14 3.0 4.0 3.5 4.5 5.0 5.5 i dd2 (ma) v dd2 (v) m c l k i n = 20 m h z , ?40 c m c l k i n = 20 m h z , +2 5 c m c l k i n = 20 m h z , +8 5 c m c l k i n = 20 m h z , +1 2 5 c m c l k i n = 10 m h z , ?40 c m c l k i n = 10 m h z , +2 5 c m c l k i n = 10 m h z , +8 5 c m c l k i n = 10 m h z , +1 2 5 c 12196-018 figure 24 . i dd2 vs. v dd2 at various temperatures and clock rates rev. b | page 12 of 24
data sheet ad7403 10 1 1 12 13 14 ?250 ?125 0 v in+ dc input (mv) 125 250 i dd2 (ma) d c i n p u t 12196-019 t a = ?40 c t a = 0 c t a = +2 5 c t a = +8 5 c t a = +1 2 5 c figure 25 . i dd2 vs. v in+ dc input at various temperatures ?60 ?40 ?20 0 20 40 60 ?320 ?240 ?160 ?80 0 80 160 240 320 i in+ (a) v in+ dc input (mv) mclkin = 5 m h z mclkin = 1 0 mh z mclkin = 2 0 mh z d c i n p u t 12196-020 figure 26 . i in+ vs. v in+ dc input at various clock rates rev. b | page 13 of 24
ad7403 data sheet terminology differential nonlinearity (dnl) dnl is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. integral nonlinearity (inl) inl is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are specified negative full scale, ?250 mv (v in + ? v in ? ), code 7168 for the 16 - bit lev el, and specified positive full scale, +250 mv (v in + ? v in ? ), code 58,368 for the 16 - bit level. offset error offset error is the deviation of the midscale code (32,768 for the 16- bit level) from the ideal v in + ? v in ? (that is, 0 v). gain error the gain error includes both positive full - scale gain error and negative full - scale gain error. positive full - scale gain error is the deviati on of the specified positive full - scale code (58,368 for the 16- bit level) from the ideal v in + ? v in ? (250 mv) after the offset error is adjusted out. negative full - scale gain error is the deviation of the specified negative full - scale code (7168 for the 1 6 - bit level) from the ideal v in + ? v in ? (?250 mv) after the offset error is adjusted out. signal -to - noise - and - distortion ratio (sinad) sinad is the measured ratio of signal to noise and distortion at the output of the adc. the signal is the rms value of th e sine wave, and noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), including harmonics, but excluding dc. signal -to - noise ratio (snr) snr is the measured ratio of signal to noise at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process: the greater the number of levels, the smaller the quantization noise. the theoretical signal - to - noise ratio for an ideal n - bit converter with a sine wave input is given by signal - to - noise ratio = ( 6.02 n + 1.76 ) db therefore, for a 12 - bit converter, the snr is 74 db. isol ation transient immunity the isolation transient immunity specifies the rate of rise and fall of a transient pulse applied across the isolation boundary, beyond which clock or data is corrupted. the ad7403 was tested using a transient pulse frequency of 100 khz. total harmonic distortion (thd) thd is the ratio of the rms sum of harmonics to the fundamental. i t is defined as 1 6 5 4 3 2 v v v v v v thd 2 2 2 2 2 log 20 (db) + + + + = v 1 is the rms amplitude of the fundamental. v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second through the sixth harmonics. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectru m (up to f s /2, excluding dc) to the rms value of the fundamental. normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it is a noise peak. effective number of bits (enob) enob is defined by enob = ( sinad ? 1.76)/6.02 bits noise free code resolution noise free code resolution represents the resolution in bits for which there is no code flicker. the noise free code resolution for an n - bit converter is defined as noise free code resolution (bits) = log 2 (2 n /peak - to - peak noise) the peak - to - peak noise in lsbs is measured with v in+ = v in? = 0 v. common - mode rejection ratio (cmrr) cmrr is defined as the ratio of the power in the adc output at 250 mv frequen cy, f, to the power of a +250 mv peak - to - peak sine wave applied to the common - mode voltage of v in+ and v in? of frequency, f s , as cmrr (db) = 10 log( pf/pf s ) where: pf is the power at frequency, f, in the adc output. pf s is the power at frequency, f s , in the adc output. power supply rejection ratio (psrr) variations in power supply affect the full - scale transition but not the linearity of the converter. psrr is the maximum change in the specified full - scale (250 mv) transition point due to a change in power supply voltage from the nominal value. rev. b | page 14 of 24
data sheet ad7403 theory of operation circuit information the ad7403 isolated - modulator convert s an analog input signal into a high speed (20 mhz maxi mum), single - bit data stream; the time average single - bit data from the modulator is directly proportional to the input signal. figure 27 shows a typical application circuit where th e ad7403 is used to provide isolation between the analog input, a current sensing resis tor or shunt, and the digital outpu t, which is then processed by a digital filter to provide an n - bit word. analog input the differential analog input of the ad7403 is implemented with a switched capacitor circuit. this circuit implements a second - order modulator stage that digitizes the input signal into a single - bit output stream. the sample clock (mclkin) provides the clock signal for the conversion process as well as the output data framing cl o ck. this clock source is externally supplied to the ad7403 . t he analog input signal is continuously sampled by the modulator and compared to an internal voltage reference. a digital stream that ac curately represents the analog input over time appears at the output of the converter (see figure 28). a differential signal of 0 v ideally results in a stream of alt er - nating 1s and 0s at the mdat output pin. this output is high 50% of the time and low 50% of the time. a differential input of 250 mv produces a stream of 1s and 0s that are high 89.06% of the time . a differential input of ?250 mv produces a stream of 1s and 0s that are high 10.94% of the time. a differential input of 320 mv ideally results in a stream of all 1s. a differential input of ? 320 mv ideally results in a stream of all 0s. the absolute full - scale range is 320 mv and the specified full - scale performance range is 250 mv, as shown in table 12. table 12 . analog input range analog input voltage input (mv) positive full - scale value +320 positive specified performance input +250 zero 0 negative specified performance input ?250 negative full - scale value ?320 - mod/ encoder nonisol a ted 5v/3v v dd1 gnd 1 v in+ v in? gnd 1 v dd1 v dd gnd v dd2 mda t mda t sinc3 fi l ter* ad7403 mclkin sda t cs sclk mclk 100nf gnd 2 decoder 1nf 10f +400v ?400v 220pf 220pf 10? 5.1v r shunt 10? decoder encoder 12196-022 1nf 10f ga ted drive circuit flo a ting power supp l y ga ted drive circuit flo a ting power supp l y mo t or *this fi l ter is implemented with an fpg a or ds p figure 27 . typical application circuit modul a t or output +fs analog input ?fs analog input analog input 12196-021 figure 28 . analog input vs. modulator output rev. b | page 15 of 24
ad7403 data sheet to reconstruct the original information, this output must be digitally filtered and decimated. a sinc3 filter is recommended because it is one order higher than that of th e ad7403 modulator , which is a second - order modulator. if a 256 decimation rate is used, the resulting 16 - bit word rate is 78.1 ksps, assuming a 20 mhz external clock frequency. see the digital filter section for more detailed information on the sinc filter implementation. figure 29 s hows the transfer function of the ad7403 relative to the 16 - bit output. 65535 58368 specified range analog input adc code 7168 ?320mv ?250mv +250mv +320mv 0 12196-023 figure 29 . filtered and decimated 16 - bit transfer function differential inputs the analog input to the modulator is a switched capacitor design. the analog signal is converted into charge by highly linear sampling capacitors. a simplified equivalent circuit diagram of the analog input is shown in figure 30 . a signal source driving the analog input must provide the charge onto the sampling capacitors every half mclkin cycle and settle to the required accuracy within the next half cycle. a b 300? v in? a b b b 300? v in+ 1.9pf 1.9pf a a mclkin 12196-024 figure 30 . analog input equivalent circuit because t he ad7403 sa mple s the differential voltage across its analog inputs, low noise performance is attained with an input circuit th at provides low common - mode noise at each input. digital output th e ad7403 mdat output driver is a slew rate limited dr iver. this driver lowers electromagnetic emissions, thus minimizing electroma gnetic interference (emi) , both conducted and radiated. rev. b | page 16 of 24
data sheet ad7403 applications informa tion current sensing appl ications th e ad7403 is ideally suited for current sensing applications where the voltage across a shunt resistor (r shunt ) is monitored. the load current flowing through an external shunt resistor produces a voltage at the input terminals of the ad7403 . the ad7403 provide s isolation between the analog input from the current sensing resistor and the digital outputs. by selecting th e appropriate shunt resistor val ue, a variety of current ranges can be monitored. choosing r shunt the shunt resistor (r shunt ) values used in conjunction with the ad7403 are determined by the specific application require - ments in terms of voltage, current, and power. small resistors minimize power dissipation, whereas low inductance resistors prevent any induced voltage spikes, and good tolerance devices reduce current variations. the final values chosen are a compromise between l ow power dissipation and accuracy. higher value resistors use the full performance input range of the adc, thus achieving maximum snr performance. low value resistors dissipate less power but do not use the full performance input range. the ad7403 , however, deliver s excellent performance, even with lower input signal levels, allowing low value shunt resistors to be used while maintaining system performance. to choose a suitable shunt resistor, f irst determine the current through the shunt. the shunt current for a 3 - phase induction motor can be expressed as pf ef v p i w rms = 73 . 1 where: i rms is the motor phase current (a rms) . p w is the motor power (watts) . v is the motor supply voltage (v ac) . ef is the motor efficiency (%) . pf is the power efficiency (%) . to determine the shunt peak sense current, i sense , consider the motor phase current and any overload that may be possible in the system. when the peak sense current is known, divide the voltag e range of t he ad7403 ( 250 mv) by the peak sense current to yield a maximum shunt value. if the power dissipation in the shunt resistor is too large, the shunt resistor can be reduced and less of the adc input range can be used. figure 31 shows the sinad performance characteristics and the enob of resolution for th e ad7403 for different input signal amplitudes. figure 32 shows the rms noise performance for d c input signal amplitudes. the performance of the ad7403 at lower input signal ranges allows smaller shunt values to be us ed while still maintaining a high level of performance and overall system efficiency. 12196-046 sinad (db) v in+ (mv) 60 65 70 75 80 85 90 0 50 100 150 200 250 11-bit enob f in = 1khz mclkin = 20mhz v dd1 = 5v v dd2 = 5v t a = 25c 12-bit enob 13-bit enob 14-bit enob ad7403 20mhz ad7403-8 20mhz figure 31 . sinad vs. v in+ ac input signal amplitude 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 ?320 ?240 ?160 ?80 0 80 160 240 320 rms noise (lsb) mclkin = 5 m h z mclkin = 1 0 m h z mclkin = 2 0 m h z v in+ dc input signa l amplitude (mv) d c i n p u t 100 k s amp l es p er d a t a p o i n t 12196-026 figure 32 . rms noise vs. v in+ dc input signal amplitude r shunt must be able to dissipate the i 2 r power losses. if the power dissipation rating of the resistor is exceeded, its value may drift or the resistor may be damaged, resulting in an open circuit. this open circuit can result in a differential voltage across the terminals of the ad7403 , in excess of the absolute maximum ratings. if i sense has a large high frequency component, choose a resistor with low inductance. voltage sensing appl ications the ad7403 can also be used for isolated voltage monitoring. for example, in motor control applications, it can be used to sense the bus voltage. in applications where the voltage being monitored exceeds the specified analog input range of the ad7403 , a voltag e divider network can be used to reduce the voltage being monitored to the required range. rev. b | page 17 of 24
ad7403 data sheet input filter in a typical use case for directly measuring the voltage across a shunt resistor, the ad7403 can be connected directly across the shunt resistor with a simple rc low - pass filter on each input. the recommended circuit conf iguration for driving the differential inputs to achieve best performance is shown in figure 33. an rc low - pass filter is placed on both the analog input pins. recom mended values for the resistors and capacitors are 10 ? and 220 pf, respectively. if possible, equalize the source impedance on each analog input to minimize offset. r v in? r v in+ c c ad7403 12196-027 figure 33 . rc low - pass filter input network the input filter configuration for t he ad7403 is not limited to the low - pass structure shown in figure 33 . the differential rc filter configuration shown in figure 34 also achieves excellent performance. recommended values for the resistors and capacitor are 22 ? and 47 p f, respectively. r v in? r v in+ c ad7403 12196-028 figure 34 . differential rc filter network figure 35 compares the typical performance for the input filter structures outlined in figure 33 and figure 34 for different resistor and capacitor values. 50 55 60 65 70 75 80 85 90 95 10 100 1000 snr (db) decim a tion r a te l ow p as s , 10? , 22 0p f di f f e re n t i al , 22? , 47 p f di f f e re n t i al , 22? , 10 n f 12196-029 f in = 1khz figure 35 . snr vs. decimation rate for different filter structures for different resistor and capacitor values digital filter the output of t he ad7403 is a continuous digital bit stream. to reconstruct the original input signal information, this output bit stream needs to be digitally filtered and decimated. a sinc filter is recommended due to its simplicity. a sinc3 filter is recommended because it is one order higher than that of the ad7403 mo dulator, which is a second - order modulator . the type of filter selecte d, the decimation rate, and the modulator clock used determines the overall system resolution and throughput rate . the higher the decimation rate, the greater the system accuracy, as ill ustr ated in figure 36 . however, there is a trade - off between accuracy and throughput rate and, therefore, higher decimation rates result in lower thr oughput solutions. note that for a given bandwidth requirement, a higher mclkin frequency can allow higher decimation rates to be used, resulting in higher snr performance. 0 10 20 30 40 50 60 70 80 90 100 10 100 1000 snr (db) decim a tion r a te s i n c 1 s i n c 2 s i n c 3 s i n c 4 12196-030 f in = 1khz figure 36 . snr vs. decimation rate for different sincx filter orders a sinc3 filter is recommended fo r the ad7403 . th is filter can be implemented on a field programmable gate array (fpga) or a digital signal processor (dsp). equation 1 describes the t ransfer function of a sinc filter. n dr z z dr z h ? ? 1 ? ) 1 ( ) 1 ( 1 ) ( 1 (1) w here : dr is the decimation rate . n is the sinc filter order. the throughput rate of the sinc filter is determined by the modulator clock and the decimation rate selected. dr mclk throughput (2) where mclk is the modulator clock frequency as the decimation rate increases, the data output size from the sinc filter increases. the output data size is expressed in equation 3. the 16 most significant bits are used to return a 16- bit result. data size = n log 2 dr (3) rev. b | page 18 of 24
data sheet ad7403 for a sinc 3 filter, the ?3 db filter response point can be derived from the filter transfer function, equation 1, and is 0.262 times the throughput rate. the filter characteristics for a third - order sinc filter are summarized in table 13. table 13 . sinc3 filter characteristics for 20 mhz mclkin decimation ratio (dr) throughput rate (khz) output data size (bits) filter response (khz) 32 625 15 163.7 64 312.5 18 81.8 128 156.2 21 40.9 256 78.1 24 20.4 512 39.1 27 10.2 the following verilog code provides an example of a sinc3 filter implementation on a xilinx? spartan ? - 6 fpga. note that the data is read on the positive clock edge. it is recommended to read in the data on the positive clock edge. the code is configurable to accommodate decimation rates from 32 to 4096. module dec256sinc24b ( input mclk1, /* used to clk filter */ input reset, /* used to reset filter */ input mdata1, /* input data to be filtered */ output reg [15:0] data, /* filtered output */ output reg data_en, input [15:0] dec_rate ); /* data is read on positive clk edge */ reg [36:0] ip_data1; reg [36:0] acc1; reg [36:0] acc2; reg [36:0] acc3; reg [36:0] acc3_d2; reg [36:0] diff1; reg [36:0] diff2; reg [36:0] diff3; reg [36:0] diff1_d; reg [36:0] diff2_d; reg [15:0] word_count; reg word_clk; reg enable; /*perform the sinc action*/ always @ (mdata1) if(mdata1==0) ip_data1 <= 37'd0; /* change 0 to a -1 for twos complement */ else ip_data1 <= 37'd1; /*accumulator (integrator) perform the accumulation (iir) at the speed of the modulator. z = one sample delay mclkout = modulators conversion bit rate */ mclkin ip_d at a1 acc1+ acc2+ acc3+ + z + z + z 12196-031 figure 37 . accumulator always @ (negedge mclk1, posedge reset) begin if (reset) begin /* initialize acc registers on reset */ acc1 <= 37'd0; acc2 <= 37'd0; acc3 <= 37'd0; end else begin /*perform accumulation process */ acc1 <= acc1 + ip_data1; acc2 <= acc2 + acc1; acc3 <= acc3 + acc2; end end /*decimation stage (mclkout/word_clk) */ always @ (posedge mclk1, posedge reset) begin if (reset) word_count <= 16'd0; else begin if ( word_count == dec_rate - 1 ) word_count <= 16'd0; else word_count <= word_count + 16'b1; end end always @ ( posedge mclk1, posedge reset ) begin if ( reset ) word_clk <= 1'b0; else begin if ( word_count == dec_rate/2 - 1 ) word_clk <= 1'b1; else if ( word_count == dec_rate - 1 ) word_clk <= 1'b0; end end /*differentiator (including decimation stage) perform the differentiation stage (fir) at a lower speed. rev. b | page 19 of 24
ad7403 data sheet z = one sample delay word_clk = output word rate */ wo r d_clk ac c3 di f f1 di f f3 + ? + ? di f f2 z ?1 ? + ? z ?1 z ?1 12196-032 figure 38 . differentiator always @ (posedge word_clk, posedge reset) begin if(reset) begin acc3_d2 <= 37'd0; diff1_d <= 37'd0; diff2_d <= 37'd0; diff1 <= 37'd0; diff2 <= 37'd0; diff3 <= 37'd0; end else begin diff1 <= acc3 - acc3_d2; diff2 <= diff1 - diff1_d; diff3 <= diff2 - diff2_d; acc3_d2 <= acc3; diff1_d <= diff1; diff2_d <= diff2; end end /* clock the sinc output into an output register word_clk = output word rate */ word_clk dat a diff3 12196-033 figure 39 . clocking sinc3 output into an output register always @ ( posedge word_clk ) begin case ( dec_rate ) 16'd32:begin data <= (diff3[15:0] == 16'h8000) ? 16'hffff : {diff3[14:0], 1'b0}; end 16'd64:begin data <= (diff3[18:2] == 17'h10000) ? 16'hffff : diff3[17:2]; end 16'd128:begin data <= (diff3[21:5] == 17'h10000) ? 16'hffff : diff3[20:5]; end 16'd256:begin data <= (diff3[24:8] == 17'h10000) ? 16'hffff : diff3[23:8]; end 16'd512:begin data <= (diff3[27:11] == 17'h10000) ? 16'hffff : diff3[26:11]; end 16'd1024:begin data <= (diff3[30:14] == 17'h10000) ? 16'hffff : diff3[29:14]; end 16'd2048:begin data <= (diff3[33:17] == 17'h10000) ? 16'hffff : diff3[32:17]; end 16'd4096:begin data <= (diff3[36:20] == 17'h10000) ? 16'hffff : diff3[35:20]; end default:begin data <= (diff3[24:8] == 17'h10000) ? 16'hffff : diff3[23:8]; end endcase end /* synchronize data output*/ always@ ( posedge mclk1, posedge reset ) begin if ( reset ) begin data_en <= 1'b0; enable <= 1'b1; end else begin if ( (word_count == dec_rate/2 - 1) && enable ) begin data_en <= 1'b1; enable <= 1'b0; end else if ( (word_count == dec_rate - 1) && ~enable ) begin data_en <= 1'b0; enable <= 1'b1; end else data_en <= 1'b0; end end endmodule rev. b | page 20 of 24
data sheet ad7403 rev. b | page 21 of 24 interfacing to adsp-cm4xx the adsp-cm4xx family of mixed-signal control processors contains on-chip sinc filter and clock generation modules for direct connection to the ad7403 mclkin and mdat pins. the adsp-cm4xx can process bit streams from four ad7403 devices using a pair of configurable sinc filters for each bit stream. the primary sinc filter of each pair produces the filtered and decimated output for the pair. the output can be decimated to any integer rate between 8 and 256 times lower than the input rate. the four secondary sinc filters are low latency filters with programmable positive and negative overrange detection comparators that can be used to detect system fault conditions figure 40 shows the typical interface between the ad7403 and the adsp-cm4xx . additional information on the configuration of the sinc filter modules in the adsp-cm4xx can be found in the an-1265 application note. sinc pair n primary secondary limit control for group n modulator clock n adsp-cm4xx 1 ad7403 1 mdat mclkin sinc0_clk0 sinc0_d0 1 additional pins omitted for clarity 12196-034 figure 40. interfacing the ad7403 to the adsp-cm4xx power supply considerations the ad7403 requires a 5 v v dd1 supply, and there are various means of achieving this. one method is to use an isolated dc-to- dc converter such as the adum6000 . this method provides a 5 v regulated dc supply across the isolation barrier. note that the inherent isolation of the adum6000 is lower than the ad7403. 12196-039 5v digital isolation barrier adum6000 ad7403 v dd1 v dd2 5v iso dc-to-dc converter figure 41. adum6000 isolated 5 v dc-to-dc regulator example another method is to regulate a dc supply on the high voltage side of the isolation barrier using a step-down dc-to-dc regulator, such as the adp2441. 12196-040 ad7403 v dd2 v dd1 5v digital 5v 4.5v to 36v adp2441 dc-to-dc switching regulator isolation barrier figure 42. adp2441 step-down dc-to-dc regulator example grounding and layout it is recommended to decouple the v dd1 supply with a 10 f capacitor in parallel with a 1 nf capacitor to gnd 1 . decouple pin 1 and pin 7 individually. decouple the v dd2 supply with a 100 nf value to gnd 2 . in applications involving high common- mode transients, ensure that board coupling across the isolation barrier is minimized. furthermore, design the board layout so that any coupling that occurs equally affects all pins on a given component side. failure to ensure equal coupling can cause voltage differentials between pins to exceed the absolute maximum ratings of the device, thereby leading to latch-up or permanent damage. place any decoupling used as close to the supply pins as possible. minimize series resistance in the analog inputs to avoid any distortion effects, especially at high temperatures. if possible, equalize the source impedance on each analog input to minimize offset. check for mismatch and thermocouple effects on the analog input printed circuit board (pcb) tracks to reduce offset drift. insulation lifetime all insulation structures eventually break down when subjected to voltage stress over a sufficiently long period. the rate of insulation degradation is dependent on the characteristics of the voltage waveform applied across the insulation. in addition to the testing performed by the regulatory agencies, analog devices carries out an extensive set of evaluations to determine the lifetime of the insulation structure within the ad7403. analog devices performs accelerated life testing using voltage levels higher than the rated continuous working voltage. acceleration factors for several operating conditions are determined. these factors allow calculation of the time to failure at the actual working voltage. the values shown in table 9 summarize the peak voltage for 20 years of service life for a bipolar, ac operating condition and the maximum vde approved working voltages.
ad7403 data sheet these tests subjected the ad7403 to continuous cross isolation voltages. to accelerate the occurrence of failures, the selected test voltages were values exceeding thos e of normal use. the time to failure values of these units were recorded and used to calculate the acceleration factors. these factors were then used to calculate the time to failure under the normal operating conditions. the values shown in table 9 are the lesser of the following two values: ? the value that ensures at least a 20 - year lifetime of continuous use. ? the maximum vde approved working voltage. note that the l ifetime of the ad7403 varies according to the waveform type imposed across the isolation barrier. the i coupler insulation structure is stressed differently, depending on whether the waveform is bipolar ac, unipolar ac, or dc. figure 43, figure 44 , and figure 45 illustrate the different isolation voltage waveforms. 0v rated peak voltage 12196-035 figure 43 . bipolar ac waveform, 50 hz or 60 hz 0v rated peak voltage 12196-036 figure 44 . unipolar ac waveform, 50 hz or 60 hz 0v rated peak voltage 12196-037 figure 45 . dc waveform rev. b | page 22 of 24
data sheet ad7403 rev. b | page 23 of 24 outline dimensions 11-15-2011-a 16 9 8 1 seating plane coplanarity 0.1 1.27 bsc 12.85 12.75 12.65 7.60 7.50 7.40 2.64 2.54 2.44 1.01 0.76 0.51 0.30 0.20 0.10 10.51 10.31 10.11 0.46 0.36 2.44 2.24 pin 1 mark 1.93 ref 8 0 0.32 0.23 0.71 0.50 0.31 45 0.25 bsc gage plane compliant to jedec standards ms-013-ac figure 46. 16-lead standard small outline package, with increased creepage [soic_ic] wide body (ri-16-2) dimensions shown in millimeters 09-17-2014-b 8 5 4 1 seating plane coplanarity 0.10 1.27 bsc 1.04 bsc 6.05 5.85 5.65 7.60 7.50 7.40 2.65 2.50 2.35 0.75 0.58 0.40 0.30 0.20 0.10 2.45 2.35 2.25 10.51 10.31 10.11 0.51 0.41 0.31 pin 1 mark 8 0 0.33 0.27 0.20 0.75 0.50 0.25 45 figure 47. 8-lead standard small outline package, with increased creepage [soic_ic] wide body (ri-8-1) dimensions shown in millimeters
ad7403 data sheet ordering guide model 1 temperature range package description package option ad7403 - 8briz ?40c to +105c 8 - lead standard small outline package, with increased creepage [soic_ic] ri -8 -1 ad7403 - 8briz -rl ?40c to +105c 8 - lead standard small outline package, with increased creepage [soic_ic] ri -8 -1 ad7403 - 8briz - rl7 ?40c to +105c 8 - lead standard small outline package, with increased creepage [soic_ic] ri -8 -1 ad7403 briz ?40c to +125c 16- lead standard small outline package, with increased creepage [soic_ic] ri -16- 2 ad7403 briz - rl ?40c to +125c 16- lead standard small outline package, with increased creepage [soic_ic] ri -16- 2 ad7403 briz - rl7 ?40c to +125c 16- lead standard small outline package, with increased creepage [soic_ic] ri -16- 2 eval - ad7403- 8fmcz ad7403 -8 evaluation board eval - ad7403 fmcz ad7403 evaluation board eval - sdp - ch1z system demonstration platform 1 z = rohs compliant part. ? 2014 C 2015 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. d12196 - 0 - 5/15(b) rev. b | page 24 of 24

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